1. Field of the Invention
The present invention relates to a field emission display, more particularly to a field emission display having a high voltage thin film transistor.
2. Description of the Prior Art
Field emission displays (FED's) are attracting significant attention because they are promising as a future flat-panel-display. The FED's include a lower plate having field emitter arrays and an upper plate coated with a fluorescent material such as phosphor. The electrons emitted from field emitters of the lower plate come into collision with the fluorescent material of the upper plate, thereby displaying a picture on a screen of the field emission display. This display, which uses a cathode luminescence of the fluorescent material, has been widely developed as a flat panel display which can be substituted for a cathode ray tube (CRT).
FIG. 1 is a schematic view illustrating a configuration of the lower plate in a conventional field emission display.
Referring to FIG. 1, the lower plate of the conventional FED's comprise a plurality of emitter arrays 10P (or pixel arrays) arranged in a matrix type, and a row driver 20P and a column driver 30P for driving each pixel. The row driver 20P and the column driver 30P control a scan signal and a data signal of the display, respectively. Each gate electrode of the emitter arrays 10P is connected to the row driver 20P and each emitter electrode of the emitter arrays 10P is connected to the column driver 30P.
FIG. 2 is a cross sectional view illustrating a conventional field emitter in FIG. 1.
As shown in FIG. 2, the conventional field emitter includes an emitter electrode 102P formed on an insulating substrate 101P, a resistance layer 103P made of an amorphous silicon layer formed on the emitter electrode 102P, cone shaped emitter tips 104P formed on a portion of the resistance layer 103P, and a gate insulating layer 105P and a gate electrode 106P surrounding the emitter tips 104P for applying electric fields to the emitter tips 104P.
The conventional field emission display has an advantage that it easily fabricated on a large glass substrate by using the electron beam evaporation method. However, it is very difficult to fabricate since the row and column drivers 20P and 30P have to supply a driving voltage more than about 50 volts to the gate electrode 106P and the emitter electrode 102P of the field emitter.
That is, because the row and column drivers 20P and 30P have a high voltage tolerance, it requires a high cost equipment and a precise process instead of a popular complementary metal-oxide-semiconductor (CMOS) fabrication technique. Accordingly, the conventional field emission display has a disadvantages that it has a high fabrication cost and a high consumption power.
Additionally, the conventional FED has an disadvantage that a line cross talk is easily caused in case that the emitter tip 104P and the gate electrode 106P are electrically short even at one pixel.